DF2378BVFQ35WV Renesas Electronics America, DF2378BVFQ35WV Datasheet - Page 39

• Manufacturer Part Number: DF2378BVFQ35WV
• Description: IC H8S/2378 MCU FLASH 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378BVFQ35WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 35MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• For Use With: EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.4 Operation............................................................................................................................ 786
16.5 Interrupt Request................................................................................................................ 801
16.6 Bit Synchronous Circuit..................................................................................................... 802
16.7 Usage Notes ....................................................................................................................... 803
Section 17 A/D Converter..................................................................................805
17.1 Features .............................................................................................................................. 805
17.2 Input/Output Pins ............................................................................................................... 807
17.3 Register Description........................................................................................................... 808
17.4 Operation............................................................................................................................ 812
17.5 Interrupt Source ................................................................................................................. 816
17.6 A/D Conversion Accuracy Definitions .............................................................................. 816
17.7 Usage Notes ....................................................................................................................... 818
16.3.4 I
16.3.5 I
16.3.6 Slave address register (SAR) ................................................................................ 784
16.3.7 I
16.3.8 I
16.3.9 I
16.4.1 I
16.4.2 Master Transmit Operation ................................................................................... 787
16.4.3 Master Receive Operation..................................................................................... 789
16.4.4 Slave Transmit Operation ..................................................................................... 791
16.4.5 Slave Receive Operation....................................................................................... 794
16.4.6 Noise Canceler ...................................................................................................... 796
16.4.7 Example of Use..................................................................................................... 796
17.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 808
17.3.2 A/D Control/Status Register (ADCSR) ................................................................ 809
17.3.3 A/D Control Register (ADCR) ............................................................................. 811
17.4.1 Single Mode.......................................................................................................... 812
17.4.2 Scan Mode ............................................................................................................ 812
17.4.3 Input Sampling and A/D Conversion Time........................................................... 813
17.4.4 External Trigger Input Timing .............................................................................. 815
17.7.1 Module Stop Mode Setting ................................................................................... 818
17.7.2 Permissible Signal Source Impedance .................................................................. 818
17.7.3 Influences on Absolute Precision.......................................................................... 819
17.7.4 Setting Range of Analog Power Supply and Other Pins ....................................... 819
17.7.5 Notes on Board Design ......................................................................................... 819
17.7.6 Notes on Noise Countermeasures ......................................................................... 819
2
2
2
2
2
2
C Bus Interrupt Enable Register (ICIER)........................................................... 780
C Bus Status Register (ICSR) ............................................................................ 782
C Bus Transmit Data Register (ICDRT) ............................................................ 785
C Bus Receive Data Register (ICDRR).............................................................. 785
C Bus Shift Register (ICDRS)............................................................................ 785
C Bus Format ..................................................................................................... 786
Rev.7.00 Mar. 18, 2009 page xxxvii of lxvi
REJ09B0109-0700