DF2378BVFQ35WV Renesas Electronics America, DF2378BVFQ35WV Datasheet - Page 477

• Manufacturer Part Number: DF2378BVFQ35WV
• Description: IC H8S/2378 MCU FLASH 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378BVFQ35WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 35MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• For Use With: EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

External Request/Cycle Steal Mode/Normal Transfer Mode: In external request mode, an
EXDMA transfer cycle is started a minimum of three cycles after a transfer request is accepted.
The next transfer request is accepted after the end of a one-transfer-unit EXDMA cycle. For
external bus space CPU cycles, at least two bus cycles are generated before the next EXDMA
cycle.
If a transfer request is generated for another channel, an EXDMA cycle for the other channel is
generated before the next EXDMA cycle.
The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The
same applies to transfer request acceptance and transfer start timing.
Figures 8.35 to 8.38 show operation timing examples for various conditions.
φ pin
EDREQ
EDRAK
Bus cycle
ETEND
EDA bit
Figure 8.35 External Request/Cycle Steal Mode/Normal Transfer Mode
1
Bus release
(No Contention/Dual Address Mode/Low Level Sensing)
EXDMA
read
EXDMA
write
Bus release
3 cycles
Rev.7.00 Mar. 18, 2009 page 409 of 1136
Section 8 EXDMA Controller (EXDMAC)
EXDMA
Last transfer cycle
read
EXDMA
write
REJ09B0109-0700
0
Bus release