DF2378BVFQ35WV Renesas Electronics America, DF2378BVFQ35WV Datasheet - Page 372

• Manufacturer Part Number: DF2378BVFQ35WV
• Description: IC H8S/2378 MCU FLASH 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378BVFQ35WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 35MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• For Use With: EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 DMA Controller (DMAC)
7.3.6
The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the
transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies
restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for
the specific channel, to prevent inadvertent rewriting of registers other than those for the channel
concerned. The restrictions applied by DMAWER are valid for the DTC.
Bit
7
to
4
3
2
1
0
Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt
request, and reactivating channel 0A. The address register and count register areas are set again
during the first DTC transfer, then the control register area is set again during the second DTC
Rev.7.00 Mar. 18, 2009 page 304 of 1136
REJ09B0109-0700
Bit Name
⎯
WE1B
WE1A
WE0B
WE0A
DMA Write Enable Register (DMAWER)
Initial Value
All 0
0
0
0
0
R/W
—
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0 and cannot be
modified.
Write Enable 1B
Enables or disables writes to all bits in DMACR1B,
bits 11, 7, and 3 in DMABCR, and bit 5 in
DMATCR.
0: Writes are disabled
1: Writes are enabled
Write Enable 1A
Enables or disables writes to all bits in DMACR1A,
and bits 10, 6, and 2 in DMABCR.
0: Writes are disabled
1: Writes are enabled
Write Enable 0B
Enables or disables writes to all bits in DMACR0B,
bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR.
0: Writes are disabled
1: Writes are enabled
Write Enable 0A
Enables or disables writes to all bits in DMACR0A,
and bits 8, 4, and 0 in DMABCR.
0: Writes are disabled
1: Writes are enabled