DF2378BVFQ35WV Renesas Electronics America, DF2378BVFQ35WV Datasheet - Page 331

IC H8S/2378 MCU FLASH 144-QFP

DF2378BVFQ35WV

Manufacturer Part Number
DF2378BVFQ35WV
Description
IC H8S/2378 MCU FLASH 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2378BVFQ35WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
35MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
For Use With
EDK2378 - DEV EVAL KIT FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2378BVFQ35WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
• Normal space access after a continuous synchronous DRAM space write access
Table 6.11 shows whether there is an idle cycle insertion or not in the case of mixed accesses to
normal space and DRAM space/continuous synchronous DRAM space.
Figure 6.80 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
If a normal space read cycle occurs after a continuous synchronous DRAM space write access
while the ICIS2 bit is set to 1 in BCR, idle cycle is inserted at the start of the read cycle. The
number of states of the idle cycle to be inserted is in accordance with the setting of bit IDLC.
It is not in accordance with the DRMI bit in DRACCR.
Figure 6.80 shows an example of idle cycle operation when the ICIS2 bit is set to 1.
DQMU, DQML
Precharge-sel
Address bus
HWR, LWR
Data bus
CKE
CAS
RAS
WE
RD
Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2)
φ
PALL ACTV
address
Column
T
Continuous synchronous
DRAM space write
p
address
address
Row
Row
T
r
NOP WRIT
T
c1
address
Column
T
c2
Idle cycle
External address space read
T
i
External address
External address
Rev.7.00 Mar. 18, 2009 page 263 of 1136
T
1
High
NOP
T
2
Section 6 Bus Controller (BSC)
T
3
READ
Synchronous
DRAM space read
T
Column address 2
c1
REJ09B0109-0700
T
Cl
NOP
T
c2

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