DF2378BVFQ35WV Renesas Electronics America, DF2378BVFQ35WV Datasheet - Page 165

• Manufacturer Part Number: DF2378BVFQ35WV
• Description: IC H8S/2378 MCU FLASH 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378BVFQ35WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 35MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• For Use With: EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.3.2
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3
After reset release, MSTPCR is initialized to H'0FFF and all modules except the DMAC,
EXDMAC and the DTC enter module stop mode.
Consequently, on-chip peripheral module registers cannot be read or written to. Register reading
and writing is enabled when module stop mode is exited.
(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction
Note: * Seven program wait states are inserted.
RES
RD
HWR, LWR
D15 to D0
Figure 4.2 Reset Sequence (Advanced Mode with On-chip ROM Disabled)
φ
Address bus
Interrupts after Reset
On-Chip Peripheral Functions after Reset Release
(1)
*
Vector fetch
(2)
High
Rev.7.00 Mar. 18, 2009 page 97 of 1136
*
(3)
(4)
Internal
processing
Section 4 Exception Handling
Prefetch of first
program instruction
*
(5)
REJ09B0109-0700
(6)