EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 668
![IC ARM920T MCU 200MHZ 352-PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-IBZ
Manufacturer Part Number
EP9312-IBZ
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-IBZ
Core Size
16/32-Bit
Package / Case
352-BGA
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Controller Family/series
(ARM9)
A/d Converter
12 Bits
No. Of I/o Pins
65
Clock Frequency
200MHz
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1260
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
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21
21-12
I
EP93xx User’s Guide
21.7.1 I
21.7 Registers
2
S Controller
Table 21-7
addressable. The left and right data registers for channels 0, 1 and 2 can be accessed by
both APB and DMA accesses. The remaining registers are concerned with control / status
information and can be only accessed through the APB bus.
2
S TX Registers
0x8082_001C
0x8082_002C
0x8082_003C
0x8082_0010
0x8082_0014
0x8082_0018
0x8082_0020
0x8082_0024
0x8082_0028
0x8082_0030
0x8082_0034
0x8082_0038
Address
summarizes the register set in the Transmitter. Each of the registers listed are
FIFO underflow
FIFO overflow
FIFO empty
FIFO Flag
FIFO full
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Width
32
32
32
32
32
32
3
2
2
1
1
1
Copyright 2007 Cirrus Logic
Reset
Value
Table 21-7. I
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Table 21-6. FIFO Flags
Interrupt and status bit
Interrupt and status bit
Transmitter
I2STXLinCtrlData
I2STXWrdLen
Sticky bit
I2STX0En
I2STX1En
I2STX2En
I2STX0Lft
I2STX1Lft
I2STX2Lft
Status
I2STX0Rt
I2STX1Rt
I2STX2Rt
I2STXCtrl
2
Name
S TX Registers
Left Transmit data register for channel 0
Right Transmit data register for channel 0
Left Transmit data register for channel 1
Right Transmit data register for channel 1
Left Transmit data register for channel 2
Right Transmit data register for channel 2
Line Control data register
Control register
Word Length
TX0 Channel Enable
TX1 Channel Enable
TX2 Channel Enable
Interrupt and status bit
Interrupt and status bit
Description
Receiver
Status bit.
Sticky bit
DS785UM1
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