EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 129
![IC ARM920T MCU 200MHZ 352-PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-IBZ
Manufacturer Part Number
EP9312-IBZ
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-IBZ
Core Size
16/32-Bit
Package / Case
352-BGA
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Controller Family/series
(ARM9)
A/d Converter
12 Bits
No. Of I/o Pins
65
Clock Frequency
200MHz
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1260
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
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DS785UM1
The normal boot function is described in
Serial boot is functionally identical to normal boot except that the SBoot bit in the SysCfg
register is set. This mode is available for a software configuration option that is readable by
the boot code.
In either normal boot or serial boot mode, once the processor starts up, it will begin to
execute the instruction at logical address 0x0000_0000. Various configuration options are
provided to select a memory device for booting from at address location 0. The options are
listed in
EECLK EEDAT BOOT1
0
0
1
1
1
1
Table
1
1
1
1
1
1
5-2.
0
0
0
0
0
0
BOOT0 ASDO CSn[7:6]
Copyright 2007 Cirrus Logic
0
0
1
0
0
0
Table 5-2. Boot Configuration Options
1
0
1
0
x
x
Chapter 4 on page
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
xx
xx
External boot fusing Sync boot mode and SDCSn3.
The media type must be either SROM or SyncFLASH.
The selection of the bus width is determined by latched
CSn[7:6] value:
16-bit
16-bit
32-bit
32-bit
External boot using Async boot mode and CSn0. The
selection of the bus width is determined by latched
CSn[7:6] value:
8-bit
16-bit
32-bit
32-bit
Internal boot from UART1.
Internal SPI boot if HeaderID is found.
Internal boot using Sync boot mode at the chip select
where the HeaderID exists. The selection of the bus
width is determined by latched CSn[7:6] value:
16-bit
16-bit
32-bit
32-bit
See memory map in
boot mode.
Internal boot using Async boot mode at the chip select
where the HeaderID exists. The selection of the bus
width is determined by latched CSn[7:6] value:
8-bit
16-bit
32-bit
32-bit
See memory map in
ASYNC boot mode.
4-1.
Boot Configuration
Table 2-7 on page 2-16
Table 2-7 on page 2-16
EP93xx User’s Guide
System Controller
for SYNC
for
5-3
5
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