EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 415

• Manufacturer Part Number: EP9312-IBZ
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IBZ

• Core Size: 16/32-Bit
• Package / Case: 352-BGA
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Controller Family/series: (ARM9)
• A/d Converter: 12 Bits
• No. Of I/o Pins: 65
• Clock Frequency: 200MHz
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1260

DS785UM1
10.2.2 Internal M2P/P2M Channel Register Map
The DMA Memory Map above includes the base address mapping for the channel registers
for each of the 10 M2P/P2M channels that are shown in the following table, the Internal
M2P/P2M Channel Register Map. This mapping is common for each channel thus offset
addresses from the bases in
Channel Base Address + 0x000C
Channel Base Address + 0x001C
Channel Base Address + 0x002C
Channel Base Address + 0x003C
0x8000_03C4 -> 0x8000_FFFC
Channel Base Address + 0x0000
Channel Base Address + 0x0004
Channel Base Address + 0x0008
Channel Base Address + 0x0010
Channel Base Address + 0x0014
Channel Base Address + 0x0018
Channel Base Address + 0x0020
Channel Base Address + 0x0024
Channel Base Address + 0x0028
Channel Base Address + 0x0030
Channel Base Address + 0x0034
Channel Base Address + 0x0038
0x8000_0340 -> 0x8000_037C
ARM920T Address
0x8000_03C0
0x8000_0380
Offset
Note:See
Note:* - write this location once to clear the interrupt (see Interrupt register description
Table 10-4. Internal M2P/P2M Channel Register Map
for which bits this rule applies to).
Table 10-3
Table 10-3
Table 10-3. DMA Memory Map
Copyright 2007 Cirrus Logic
M2P Channel 8 Registers (Tx)
“INTERRUPT”
“CURRENTx”
“CURRENTx”
DMA Global Interrupt register
“CONTROL”
“MAXCNTx”
“MAXCNTx”
“PPALLOC”
Register
“REMAIN”
“STATUS”
Reserved
Reserved
Reserved
Reserved
Reserved
DMA Channel Arbitration
“BASEx”
“BASEx”
Name
for Channel Base Addresses
Description
Not Used
register
are shown in
R/W TC *
Access
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
Table
Bits
16
16
32
32
16
32
32
6
3
4
8
Channel Base Address
10-4.
(see register description)
Channel dependant
0x8000_03C4
0x8000_0340
Reset Value
0
0
0
0
0
0
0
0
0
0
EP93xx User’s Guide
DMA Controller
10-21
10