EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 535
![IC ARM920T MCU 200MHZ 352-PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-IBZ
Manufacturer Part Number
EP9312-IBZ
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-IBZ
Core Size
16/32-Bit
Package / Case
352-BGA
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Controller Family/series
(ARM9)
A/d Converter
12 Bits
No. Of I/o Pins
65
Clock Frequency
200MHz
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1260
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
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Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
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DS785UM1
14.4.7 Aborts
incoming address consisting entirely of “1”s, that is, 0xFF or 0xFFFF, will always match, as it
is expected to be the broadcast address. For packets whose addresses do not match, the
HDLC receiver will generate no interrupts, modify no status bits, and place no data in the
receive FIFO.
If a packet is aborted or is too short, or if using Manchester encoding and the receiver DPLL
loses the carrier signal, the CPU will see at least some part of the packet in the receive FIFO.
In all cases, reading the last byte of the packet from the receive FIFO will set the EOF and
RAB bits in the UART1HDLCSts (and possibly generate an interrupt). In the case of an abort
indicated by an HDLC transmitter, that is, an escape-closing flag sequence in asynchronous
mode or an all “1”s byte in synchronous mode, all bytes received in the frame will appear in
the receive FIFO.
In asynchronous mode, if the abort is caused by a framing error (a missing stop bit), all bytes
up to and including the misframed byte will appear in the receive FIFO. Reading the last byte
will also set the UART1HDLCSts.FRE bit.
In synchronous mode, if the abort is caused by a misaligned flag or a series of seven
consecutive “1”s, all bytes except the one containing the bit after the sixth “1” will appear in
the receive FIFO. If the abort is caused by the receiver DPLL losing synchronization with a
Manchester encoded bit stream, the UART1HDLCSts.DPLLE bit is set.
Finally, if the packet is too short, that is, there are not enough received bytes to hold the
specified number of address and CRC bytes, the entire packet will appear in the receive
FIFO. In all cases, the packet is illegal and will be ignored by the CPU.
AME
00
01
10
11
One byte address
Two byte address
No matching
Function
Undefined
Match
Table 14-3. HDLC Receive Address Matching Modes
Copyright 2007 Cirrus Logic
NOT ((AMV[31:24] XOR ADDR) AND AMSK[31:24]) OR
NOT ((AMV[23:16] XOR ADDR) AND AMSK[23:16]) OR
NOT ((AMV[15:8] XOR ADDR) AND AMSK[15:8]) OR
NOT ((AMV[7:0] XOR ADDR) AND AMSK[7:0]) OR
ADDR = 0xFF
NOT ((AMV[31:16] XOR ADDR) AND AMSK[31:16]) OR
NOT ((AMV[15:0] XOR ADDR) AND AMSK[15:0]) OR
ADDR = 0xFFFF
Address Match Test
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
14-13
14
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