EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 318

• Manufacturer Part Number: EP9312-IBZ
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IBZ

• Core Size: 16/32-Bit
• Package / Case: 352-BGA
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Controller Family/series: (ARM9)
• A/d Converter: 12 Bits
• No. Of I/o Pins: 65
• Clock Frequency: 200MHz
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1260

9
9-16
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9.2.3 Receive Status Queue
The receive status queue is used to pass receive status from the MAC to the Host. In
operation, the receive status queue is similar to the receive descriptor queue. It is a circular
queue in contiguous memory space. The location and size of the queue are set at
initialization by writing to the Receive Status Queue Base Address and the Receive Status
Queue Base Length registers. The base address must point to a word aligned memory
location. The length is set to the actual status queue length (in bytes) and should not exceed
64 Kbytes total. The number of status entries should be an integral power-of-two (2, 4, 8, 16,
etc.), or the Receive Descriptor Processor may not work properly, and the MAC/Ethernet may
stop receiving frames. The Current Address must be set to point to the first status entry to be
used. This would normally be the first entry (same value as the base address).
When the receive status queue initialization is complete, the Receive Status Enqueue
register is used by the Host to pass free status locations to the MAC. To simplify this process
the Host writes the number of additional free status locations available to the enqueue
register. The MAC adds the additional count to the previously available location to determine
the total number of available receive status entries. When the MAC writes status to the
queue, it subtracts the number written from this total. The current value of the total receive
status entries is available by reading the enqueue register.
No more than 255 status entries may be added in one write. If a number greater than this
needs to be written, the write should be broken up into more than one operation (that is, to
add 520 status entries: write 255, then write 255, finally write 10).
Copyright 2007 Cirrus Logic
DS785UM1