EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 460
![IC ARM920T MCU 200MHZ 352-PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-IBZ
Manufacturer Part Number
EP9312-IBZ
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-IBZ
Core Size
16/32-Bit
Package / Case
352-BGA
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Controller Family/series
(ARM9)
A/d Converter
12 Bits
No. Of I/o Pins
65
Clock Frequency
200MHz
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1260
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
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11
HcHCCA
HcPeriodCurrentED
11-20
Universal Serial Bus Host Controller
EP93xx User’s Guide
31
15
31
15
Address:
Default:
Definition:
Bit Description:
Address:
30
14
30
14
29
13
29
13
28
12
28
12
FNO:
RHSC:
OC:
MIE:
0x8002_0018
0x0000_0000
Base physical address of the Host Controller Communication Area.
RSVD:
AD:
0x8002_001C
AD
27
27
11
11
26
10
26
10
AD
Copyright 2007 Cirrus Logic
25
25
9
9
FrameNumberOverflow: Disable interrupt generation due
to Frame Number Overflow.
RootHubStatusChange: Disable interrupt generation due
to Ownership Change.
OwnershipChange. Enable interrupt generation due to
Ownership Change.
Master Interrupt Enable: A zero written to this field is
ignored by HC. A one written to this field disables interrupt
generation due to events specified in the other bits of this
register. This field is set after a hardware or software reset.
Reserved. Unknown During Read.
HCCA. Base physical address of the Host Controller
Communication Area.
24
24
8
8
AD
AD
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
RSVD
19
19
3
3
18
18
2
2
RSVD
17
17
1
1
DS785UM1
16
16
0
0
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