EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 571

• Manufacturer Part Number: EP9312-IBZ
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IBZ

• Core Size: 16/32-Bit
• Package / Case: 352-BGA
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Controller Family/series: (ARM9)
• A/d Converter: 12 Bits
• No. Of I/o Pins: 65
• Clock Frequency: 200MHz
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1260

UART2Flag
DS785UM1
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
SIRLP:
SIREN:
UARTE:
0x808D_0018 - Read/Write
0x0000_0000
UART Flag Register
RSVD:
TXFE:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
SIR Low Power Mode. This bit selects the IrDA encoding
mode. If this bit is cleared to 0, low level bits are
transmitted as an active high pulse with a width of 3/16
the bit period. If this bit is set to “1”, low level bits are
transmitted with a pulse width which is 3 times the period
of the IrLPBaud16 input signal, regardless of the selected
bit rate. Setting this bit uses less power, but may reduce
transmission distances.
SIR Enable. If this bit is set to “1”, the IrDA SIR
encoder/decoder is enabled. This bit has no effect if the
UART is not enabled by bit 0 being set to “1”. When the
IrDA SIR encoder/decoder is enabled, data is transmitted
and received on nSIROUT and SIRIN. UARTTXD remains
in the marking state (set to “1”). Signal transitions on
UARTRXD or modem status inputs will have no effect.
When the IrDA SIR encoder/decoder is disabled,
nSIROUT remains cleared to 0 (no light pulse generated),
and signal transitions on SIRIN will have no effect.
UART Enable. If this bit is set to “1”, the UART is enabled.
Data transmission and reception occurs for UART signals.
Reserved. Unknown During Read.
Transmit FIFO Empty. The meaning of this bit depends on
the state of the FEN bit in the UART2LinCtrlHigh register.
If the FIFO is disabled, this bit is set when the transmit
holding register is empty. If the FIFO is enabled, the TXFE
bit is set when the transmit FIFO is empty.
24
8
RSVD
TXFE
23
7
RXFF
22
6
TXFF
21
5
RXFE
20
4
BUSY
19
3
EP93xx User’s Guide
DCD
18
2
DSR
17
1
UART2
15-13
th
CTS
16
0
of
15