EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 573

• Manufacturer Part Number: EP9312-IBZ
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IBZ

• Core Size: 16/32-Bit
• Package / Case: 352-BGA
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Controller Family/series: (ARM9)
• A/d Converter: 12 Bits
• No. Of I/o Pins: 65
• Clock Frequency: 200MHz
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1260

UART2IrLowPwrCntr
DS785UM1
31
15
Default:
Definition:
Bit Descriptions:
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x0000_0000
UART Interrupt Identification and Interrupt Clear Register. Interrupt status is
read from UART2IntIDIntClr. A write to UART2IntIDIntClr clears the modem
status interrupt. All the bits are cleared to 0 when reset.
RSVD:
RTIS:
TIS:
RIS:
MIS:
0x808D_0020 - Read/Write
0x0000_0000
UART IrDA Low Power Divisor Register. This is an 8-bit read/write register
that stores the low-power counter divisor value used to generate the
IrLPBaud16 signal by dividing down of UARTCLK. All the bits are cleared to 0
when reset.
RSVD:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Receive Timeout Interrupt Status. This bit is set to “1” if the
receive timeout interrupt is asserted.
Transmit Interrupt Status. This bit is set to “1” if the
transmit interrupt is asserted.
Receive Interrupt Status. This bit is set to “1” if the receive
interrupt is asserted.
Modem Interrupt Status. This bit is set to “1” if the modem
status interrupt is asserted.
Reserved. Unknown During Read.
24
8
RSVD
23
7
22
6
21
5
20
4
ILPDV
19
3
EP93xx User’s Guide
18
2
17
1
UART2
15-15
16
0
15