EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 294
![IC ARM920T MCU 200MHZ 352-PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-IBZ
Manufacturer Part Number
EP9312-IBZ
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-IBZ
Core Size
16/32-Bit
Package / Case
352-BGA
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Controller Family/series
(ARM9)
A/d Converter
12 Bits
No. Of I/o Pins
65
Clock Frequency
200MHz
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1260
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
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8
BLOCKCTRL
8-30
Graphics Accelerator
EP93xx User’s Guide
INTEOI
31
15
Address:
Default:
Mask:
Definition:
Bit Descriptions:
BG
30
14
REMAP
29
13
28
12
D1
0x8004_0024 - Read/Write
0x0000_0000
0x001F_FFFF
Block Function Control Register
RSVD:
PACKD:
P:
P2
0
0
0
D0
27
11
P1
RSVD
0
0
1
M1
26
10
Table 8-23. Pixel Mode Encoding
Copyright 2007 Cirrus Logic
M0
25
9
P0
0
1
0
Reserved - Unknown during read
Packed Image Bit - Read/Write
This bit is normally ‘0’ to indicate that the source and
destination images during a Block Copy function are the
same size.
When this bit is '1', the a block transfer image source is
stored in packed format. Packed format indicates that the
source image is not the same dimensions as the
destination image, and that source information transfers
are whole words with the possible exceptions of the
beginning and ending words. This allows images to be
packed into any square configuration of whole words,
including a serial stream.
Bits Per Pixel - Read/Write
The value of this field, as shown in
the pixel mode (depth) that is used for Graphics
Accelerator functions. The Raster Engine has a similar
pixel depth field, but it’s value is independent from this P
value and may be either different or the same.
SYDIR
24
8
SXDIR
23
7
8 bits per pixel
Pixel Mode
4 bit per pixel
DYDIR
not defined
22
6
DXDIR
21
5
PACKD
LINE
20
4
Table
FILL
19
3
TRANS
8-23, specifies
18
P
2
INTEN
17
1
DS785UM1
ERROR
EN
16
0
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