SAK-C505CA-4EM CA Infineon Technologies, SAK-C505CA-4EM CA Datasheet - Page 53

IC MCU 8BIT 32KB OTP MQFP-44-2

SAK-C505CA-4EM CA

Manufacturer Part Number
SAK-C505CA-4EM CA
Description
IC MCU 8BIT 32KB OTP MQFP-44-2
Manufacturer
Infineon Technologies
Series
C5xx/C8xxr
Datasheet

Specifications of SAK-C505CA-4EM CA

Core Processor
C500
Core Size
8-Bit
Speed
20MHz
Connectivity
CAN, EBI/EMI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
4.25 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-BQFP
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
CAN, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
34
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Packages
PG-MQFP-44
Max Clock Frequency
20.0 MHz
Sram (incl. Cache)
1.25 KByte
Can Nodes
1
A / D Input Lines (incl. Fadc)
8
Program Memory
32.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
K505CA4EMCANP
K505CA4EMCAXT
SAK-C505CA-4EMCA
SAK-C505CA-4EMCAINTR
SAK-C505CA-4EMCATR
SAK-C505CA-4EMCATR
SAKC505CA4EMCAXT
SP000106397
Power Saving Modes
The C505 provides two basic power saving modes, the idle mode and the power down mode.
Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate
in normal operating mode and it can be also used for further power reduction in idle mode.
In the power down mode of operation,
be ensured, however, that
is restored to its normal operating level, before the power down mode is terminated.
a general overview of the entry and exit procedures of the power saving modes.
Table 10
Power Saving Modes Overview
Mode
Idle Mode
Power Down Mode
Slow Down Mode
Data Sheet
– Idle mode
– Power down mode
– Slow down mode
In the idle mode the main oscillator of the C505 continues to run, but the CPU is gated off from
the clock signal. All peripheral units are further provided with the clock. The CPU status is
preserved in its entirety. The idle mode can be terminated by any enabled interrupt of a
peripheral unit or by a hardware reset.
The operation of the C505 is completely stopped and the oscillator is turned off. This mode is
used to save the contents of the internal RAM with a very low standby current. Power down
mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/
INT0.or P4.1/RXDC.
The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by 32. This slows down all parts of the controller, the CPU and all
peripherals, to 1/32-th of their normal operating frequency. Slowing down the frequency
significantly reduces power consumption.
ORL PCON, #01H
Entering
(Instruction
Example)
ORL PCON, #20H
ORL PCON, #02H
ORL PCON, #40H
ORL PCON,#10H
V
DD
is not reduced before the power down mode is invoked, and that
V
DD
can be reduced to minimize power consumption. It must
Leaving by
Ocurrence of an
interrupt from a
peripheral unit
Hardware Reset
Hardware Reset
Short low pulse at
pin P3.2/INT0 or
P4.1/RXDC
ANL PCON,#0EFH
or
Hardware Reset
49
C505/C505C/C505A/C505CA
Remarks
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock
Oscillator is stopped;
contents of on-chip RAM and
SFR’s are maintained;
Oscillator frequency is
reduced to 1/32 of its nominal
frequency
Table 10
12.00
gives
V
DD

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