SAK-C505CA-4EM CA Infineon Technologies, SAK-C505CA-4EM CA Datasheet - Page 28

IC MCU 8BIT 32KB OTP MQFP-44-2

SAK-C505CA-4EM CA

Manufacturer Part Number
SAK-C505CA-4EM CA
Description
IC MCU 8BIT 32KB OTP MQFP-44-2
Manufacturer
Infineon Technologies
Series
C5xx/C8xxr
Datasheet

Specifications of SAK-C505CA-4EM CA

Core Processor
C500
Core Size
8-Bit
Speed
20MHz
Connectivity
CAN, EBI/EMI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
4.25 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-BQFP
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
CAN, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
34
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Packages
PG-MQFP-44
Max Clock Frequency
20.0 MHz
Sram (incl. Cache)
1.25 KByte
Can Nodes
1
A / D Input Lines (incl. Fadc)
8
Program Memory
32.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
K505CA4EMCANP
K505CA4EMCAXT
SAK-C505CA-4EMCA
SAK-C505CA-4EMCAINTR
SAK-C505CA-4EMCATR
SAK-C505CA-4EMCATR
SAKC505CA4EMCAXT
SP000106397
Table 4
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)
Addr
D9 H
D9 H
DA H
DA H
DC H
E0 H
E8 H
F0 H
FC H
FD H
FE H
Data Sheet
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
4) These are read-only registers
5) The content of this SFR varies with the actual of the step C505 (eg. 01
6) C505 / C505C only
7) C505A / C505CA only
8) C505 / C505C AB step only
9) C505A-4E / C505CA-4E BA step only (11
10) C505A-4R / C505CA-4R BB step only (32
2)
2)
2)
3)4)
3)4)
3)4)
ADDAT
ADST
ADDATL
Register Content
ADDATH
ADCON1 01XX-
ACC
P4
B
VR0
VR1
VR2
7)
7)
5)
6)
6)
after
Reset
00 H
00 H
XXXX-
XXXX B
00XX-
XXXX B
X000 B
00 H
XXXX-
XX11 B
00 H
C5 H
05 H
01 H
12 H
33 H
8)
9)
10)
1)
Bit 7
.7
.9
.1
ADCL1 ADCL0 –
.7
.7
1
0
.7
Bit 6
.6
.8
.0
.6
.6
1
0
.6
H
H
for the AA step)
for the BA step)
Bit 5
.5
.7
.5
.5
0
0
.5
24
Bit 4
.4
.6
.4
.4
0
0
.4
C505/C505C/C505A/C505CA
Bit 3
.3
.5
.3
.3
0
0
.3
H
or 11
H
Bit 2
.2
.4
MX2
.2
.2
1
1
.2
or 21
H
for the first step)
Bit 1
.1
.3
MX1
.1
RXDC
.1
0
0
.1
Bit 0
.0
.2
MX0
.0
TXDC
.0
1
1
.0
12.00

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