MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 61

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

operation sizes, and assembler syntax. For two-operand instructions, the first operand is
generally the source operand and the second is the destination.
Because the ColdFire architecture provides an upgrade path for 68K customers, its
instruction set supports most of the common 68K opcodes. A majority of the instructions
are binary compatible or optimized 68K opcodes. This feature, when coupled with the code
conversion tools from third-party developers, generally minimizes software porting issues
for customers with 68K applications.
The following list summarizes new and enhanced instructions of Revision B ISA:
• New instructions:
• Enhancements to existing Revision A instructions:
— INTOUCH loads blocks of instructions to be locked in the instruction cache.
— MOV3Q.L moves 3-bit immediate data to destination location.
— MVS.{B,W} sign-extends the source operand and moves it to destination
— MVZ.{B,W} zero-fills the source operand and moves it to destination register.
— SATS.L updates bit 31 of destination register depending on CCR overflow bit.
— TAS.B tests and set byte operand being addressed.
— Longword support for branch instructions (Bcc, BRA, BSR)
— Byte and word support for compare instructions (CMP, CMPI)
— Byte and longword support for MOVE.x where the source is of type #<data> and
register.
the destination is of type d16(Ax); that is, move.b #<data>, d16(Ax)
Programming Model, Addressing Modes, and Instruction Set
Chapter 1. Overview
1-17