MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 130

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Power Management
; +0
; +4
; +8
; +12
; +16
; +20
; +24
loop:
4.6 Power Management
Because processor memory references may be simultaneously sent to an SRAM module
and cache, power can be minimized by configuring RAMBAR address space masks as
precisely as possible. For example, if an SRAM is mapped to the internal instruction bus
and contains instruction data, setting the ASn mask bits associated with operand references
can decrease power dissipation. Similarly, if the SRAM contains data, setting ASn bits
associated with instruction fetches minimizes power.
Table 4-2 shows typical RAMBAR configurations.
4.7 Cache Overview
This section describes the MCF5407 cache implementation, including organization,
configuration, and coherency. It describes cache operations and how the cache interacts
with other memory structures.
4-6
.
move.l
movec.l
move.l
lea.l
add.l
move.l
asr.l
.align
movem.l
movem.l
lea.l
lea.l
subq.l
bne.b
movem.l
lea.l
rts
saved d2
saved d3
saved d4
returnPc
pointer to source operand
destinationOffset
bytesToMove
Table 4-2. Examples of Typical RAMBAR Settings
Code only
Data only
Both code and data
Data Contained in SRAM
RAMBASE+RAMFLAGS,a0
a0,rambar0
16(a7),a0
RAMBASE,a1
20(a7),a1
24(a7),d4
#4,d4
4
(a0),#0xf
#0xf,(a1)
16(a0),a0
16(a1),a1
#1,d4
loop
(a7),#0x1c
12(a7),a7
MCF5407 User’s Manual
;define RAMBAR0 contents
;load it
;load argument defining *src
;memory pointer to RAM base
;include destinationOffset
;load byte count
;divide by 16 to convert to loop count
;force loop on 0-mod-4 address
;read 16 bytes from source
;store into RAM destination
;increment source pointer
;increment destination pointer
;decrement loop counter
;if done, then exit, else continue
;restore d2/d3/d4 registers
;deallocate temporary space
RAMBAR[5–0]
0x2B
0x35
0x21