MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 154

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Cache Operation Summary
Write hit
(write-
through)
Cache
invalidate
Cache
push
The following tables present the same information as Table 4-7, organized by the current
state of the cache line. In Table 4-8 the current state is invalid.
In Table 4-9 the current state is valid.
4-30
Access
Table 4-8. Data Cache Line State Transitions (Current State Invalid)
WI4
(C,W)I5 No action;
(C,W)I6
(C,W)I7
Read miss
Read hit
Write miss (copyback)
Write miss (write-through)
Write hit (copyback)
Write hit (write-through)
Cache invalidate
Cache push
Cache push
Table 4-7. Data Cache Line State Transitions (Continued)
Invalid (V = 0)
Not possible.
stay in invalid state.
No action;
stay in invalid state.
Access
WV4
(C,W)V5 No action;
(C,W)V6 No action;
(C,W)V7 No action;
(C,W)I1 Read line from memory and update cache;
(C,W)I2 Not possible
CI3
WI3
CI4
WI4
(C,W)I5 No action;
(C,W)I6 No action;
(C,W)I7 No action;
MCF5407 User’s Manual
Valid (V = 1, M = 0)
supply data to processor;
go to valid state.
Read line from memory and update cache;
write data to cache;
go to modified state.
Write data to memory;
stay in invalid state.
Not possible
Not possible
stay in invalid state.
stay in invalid state.
stay in invalid state.
Write data to memory and
to cache;
stay in valid state.
go to invalid state.
go to invalid state.
stay in valid state.
Current State
Response
WD4 Write data to memory and
CD5 No action (modified data
CD6 Push modified line to
CD7 Push modified line to
Modified (V = 1, M = 1)
to cache;
go to valid state.
Cache mode changed for
the region corresponding to
this line. To avoid this state,
execute a CPUSHL
instruction or set
CACR[DCINVA,ICINVA]
before switching modes.
lost);
go to invalid state.
memory;
go to invalid state.
memory;
go to valid state.