MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 177

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.4.9 Resulting Set of Possible Trigger Combinations
The resulting set of possible breakpoint trigger combinations consist of the following
options where || denotes logical OR, && denotes logical AND, and {} denotes an optional
additional trigger term:
One-level triggers of the form:
if
if
if
if
if
if
Two-level triggers of the form:
if
if
if
if
if
if
if
21/5
20–18/
4–2
20/4
19/3
18/2
17–16,
1–0
Bits
Name
DI
EAx
—
(PC_breakpoint)
(PC_breakpoint||Address_breakpoint{&& Data_breakpoint})
(PC_breakpoint||Address_breakpoint{&& Data_breakpoint}
(Address_breakpoint
((Address_breakpoint
(Address1_breakpoint
(PC_breakpoint)
then if
(PC_breakpoint)
then if
(PC_breakpoint)
then if
(Address_breakpoint
then if
(Address1_breakpoint
then if
(Address_breakpoint
then if
(Address1_breakpoint
Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint
comparators. This can develop a trigger based on the occurrence of a data value other than the
DBR1 contents.
Enable address bits. Setting an EAx bit enables the corresponding address breakpoint. If all three
bits are cleared, this breakpoint is disabled.
EAI
EAR
EAL
Reserved, should be cleared.
||
||
||
Table 5-18. XTDR Field Descriptions (Continued)
Enable address breakpoint inverted. Breakpoint is based outside the range between
ABLR1 and ABHR1.
Enable address breakpoint range. Breakpoint is based on the range defined between
ABLR1 and ABHR1.
Enable address breakpoint low. The breakpoint is based on the address in ABLR1.
Address1_breakpoint{&& Data1_breakpoint})
(Address1_breakpoint{&& Data1_breakpoint}))
Address1_breakpoint{&& Data1_breakpoint})
(Address1_breakpoint{&& Data1_breakpoint})
(Address1_breakpoint{&& Data1_breakpoint})
(Address_breakpoint{&& Data_breakpoint})
(PC_breakpoint)
(Address_breakpoint{&& Data_breakpoint})
(Address_breakpoint{&& Data_breakpoint}
Chapter 5. Debug Support
{&& Data_breakpoint})
{&& Data_breakpoint})
{&& Data1_breakpoint})
{&& Data_breakpoint})
{&& Data1_breakpoint})
{&& Data_breakpoint})
{&& Data1_breakpoint})
Description
Programming Model
5-21