MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 419

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.4.3 Bus Driven (BD)
The MCF5407 asserts BD to indicate that it is the current master and is driving the bus. The
MCF5407 behaves as follows:
17.5 Clock and Reset Signals
The clock and reset signals configure the MCF5407 and provide interface signals to the
external system.
17.5.1 Reset In (RSTI)
Asserting RSTI causes the MCF5407 to enter reset exception processing. When RSTI is
recognized, BR and BD are negated and the address bus, data bus, TT, SIZ, R/W, AS, and
TS are three-stated. RSTO is asserted automatically when RSTI is asserted.
17.5.2 Clock Input (CLKIN)
CLKIN is the MCF5407 input clock frequency to the on-board phase-locked-loop (PLL)
clock generator. CLKIN is used to internally clock or sequence the MCF5407 internal bus
interface at a selected multiple of the input frequency used for internal module logic.
CLKIN should be used as the bus timing reference.
17.5.3 Bus Clock Output (BCLKO)
The internal PLL generates BCLKO. It has the same frequency as CLKIN, which is used
as the bus timing reference by the external devices. BCLKO is provided for compatibility
with earlier devices.
17.5.4 Reset Out (RSTO)
After RSTI is asserted, the PLL temporarily loses its lock, during which time RSTO is
asserted. When the PLL regains its lock, RSTO negates again. This signal can be used to
reset external devices.
• If the MCF5407 is the bus master but is not using the bus, BD is asserted.
• If the MCF5407 loses mastership during a transfer, it completes the last transfer of
• If the MCF5407 loses bus mastership during an idle clock cycle, it three-states all
• BD cannot be negated unless BG is negated.
the access, negates BD, and three-states all bus signals on the rising edge of CLKIN.
bus signals on the rising edge of CLKIN.
Chapter 17. Signal Descriptions
Clock and Reset Signals
17-13