MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 418

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Interrupt Control Signals
17.3 Interrupt Control Signals
The interrupt control signals supply the external interrupt level to the MCF5407 device.
17.3.1 Interrupt Request (IRQ1/IRQ2, IRQ3/IRQ6, IRQ5/IRQ4,
The IRQ1, IRQ3, IRQ5, and IRQ7 signals are the default interrupt request signals (IRQn).
However, by setting the appropriate bit in the interrupt port assignment register (IRQPAR),
IRQ1, IRQ3, and IRQ5 can be changed to function as IRQ2, IRQ6, and IRQ4, respectively.
See Section 9.2.4, “Interrupt Port Assignment Register (IRQPAR).”
17.4 Bus Arbitration Signals
The bus arbitration signals provide the external bus arbitration control for the MCF5407.
17.4.1 Bus Request (BR)
The BR output indicates to an external arbiter that the processor is requesting to be bus
master for one or more bus cycles. BR is negated when the MCF5407 begins an access to
the external bus with no other internal accesses pending. BR remains negated until another
internal request occurs.
17.4.2 Bus Grant (BG)
An external arbiter asserts the BG input to indicate that the MCF5407 can take control of
the bus on the next rising edge of CLKIN. When the arbiter negates BG, the MCF5407 will
release the bus as soon as the current transfer completes. The external arbiter must not grant
the bus to any other master until both BD and BG are negated.
17-12
and IRQ7)
Table 17-10. TM[2:0] Encodings for TT = 11 (Interrupt Level)
TM[2:0]
000
001
010
011
100
101
110
111
MCF5407 User’s Manual
CPU Space
Interrupt level 1 acknowledge
Interrupt level 2 acknowledge
Interrupt level 3 acknowledge
Interrupt level 4 acknowledge
Interrupt level 5 acknowledge
Interrupt level 6 acknowledge
Interrupt level 7 acknowledge
Transfer Modifier