MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 443

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 18-17 shows a line burst write with one wait-state insertion.
Figure 18-18 shows a burst-inhibited line write. The external device executes a basic write
cycle while determining that a line is being transferred. The external device uses fast
termination to end each subsequent transfer.
OE, BWE
18.4.7.4 Transfers Using Mixed Port Sizes
Figure 18-19 shows timing for a longword read from an 8-bit port using external
termination. Figure 18-20 shows the same transfer with internal termination. For both,
SIZ[1:0] change only at the start of a new transfer because this burst is implemented as one
TM[2:0], TT[1:0]
R/W, TIP
AS, CSx
Figure 18-17. Line Write Burst (3-2-2-2) with One Wait State, Internal Termination
SIZ[1:0]
TM[2:0]
D[31:0]
A[31:0]
TT[1:0]
CLKIN
OE, BWE
TS
TA
R/W, TIP
AS, CSx
SIZ[1:0]
D[31:0]
A[31:0]
CLKIN
TS
TA
Figure 18-18. Line Write Burst-Inhibited, Internal Termination
S0
S0 S1 S2 S3
S1
A[3:2] = 00
S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5
Basic
Line
Write
Write
Chapter 18. Bus Operation
WS
S4 S5
A[3:2] = 01
Fast
Write
Write
WS
S6
A[3:2] = 10
Longword
S7
Fast
Write
Write
WS
S8
Data Transfer Operation
A[3:2] = 11
S9
Fast
Write
Write
WS
S10
S11
18-15