DF2398TE20V Renesas Electronics America, DF2398TE20V Datasheet - Page 621
![IC H8S MCU FLASH 256K 120TQFP](/photos/12/21/122170/df2398te20v_sml.jpg)
DF2398TE20V
Manufacturer Part Number
DF2398TE20V
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2398TE20V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 621 of 1049
- Download datasheet (5Mb)
Notes on Use of User Mode:
When the chip comes out of reset in boot mode, it measures the low-level period of the input at the SCI’s RxD1 pin.
The reset should end with RxD1 high. After the reset ends, it takes approximately 100 states before the chip is ready to
measure the low-level period of the RxD1 pin.
In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks
are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming
is performed, or if the program activated in user program mode is accidentally erased.
Interrupts cannot be used while the flash memory is being programmed or erased.
The RxD1 and TxD1 pins should be pulled up on the board.
Before branching to the programming control program (RAM area H'FFE400), the chip terminates transmit and
receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit
rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state (P31DDR = 1,
P31DR = 1).
The contents of the CPU’s internal general registers are undefined at this time, so these registers must be initialized
immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used
implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program.
Initial settings must also be made for the other on-chip registers.
Boot mode can be entered by making the pin settings shown in table 19-14 and executing a reset-start.
Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the FWE pin and mode
pins, and executing reset release*
Do not change the mode pin input levels in boot mode, and do not drive the FWE pin low while the boot program is
being executed or while flash memory is being programmed or erased*
Notes: 1. The boot program area cannot be used until a transition is made to the execution state
2. The area from H'FFFB80 to H'FFFBFF (128 bytes) is used by the boot program.
for the programming control program transferred to RAM. Note that the boot program
remains stored in this area after a branch is made to the programming control program.
The area from H'FFE400 to H'FFFB7F can be used by the programming control program.
1
H'FFDC00
H'FFE3FF
H'FFFB7F
H'FFFBFF
. Boot mode can also be cleared by a WDT overflow reset.
Figure 19-17 RAM Areas in Boot Mode
control program
(128 bytes)*
Boot program
Programming
(2 kbytes)
(6 kbytes)
area*
area
1
2
2
.
Rev.6.00 Oct.28.2004 page 591 of 1016
REJ09B0138-0600H
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