DF2398TE20V Renesas Electronics America, DF2398TE20V Datasheet - Page 475
![IC H8S MCU FLASH 256K 120TQFP](/photos/12/21/122170/df2398te20v_sml.jpg)
DF2398TE20V
Manufacturer Part Number
DF2398TE20V
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2398TE20V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 475 of 1049
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12.3.5
If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B’100, the 8-bit timers of the two channels are cascaded. With
this configuration, a single 16-bit timer could be used (16-bit timer mode) or compare matches of the 8-bit channel 0 could
be counted by the timer of channel 1 (compare match counter mode). In this case, the timer operates as below.
16-Bit Counter Mode: When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions as a single 16-bit timer
with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
Compare Match Counter Mode: When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts compare match A’s for
channel 0.
Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts,
output from the TMO pin, and counter clear are in accordance with the settings for each channel.
Note on Usage: If the 16-bit counter mode and compare match counter mode are set simultaneously, the input clock
pulses for TCNT0 and TCNT1 are not generated and thus the counters will stop operating. Software should therefore
avoid using both these modes.
Setting of compare match flags
Counter clear specification
Pin output
The CMF flag in TCSR0 is set to 1 when a 16-bit compare match event occurs.
The CMF flag in TCSR1 is set to 1 when a lower 8-bit compare match event occurs.
If the CCLR1 and CCLR0 bits in TCR0 have been set for counter clear at compare match, the 16-bit counter
The settings of the CCLR1 and CCLR0 bits in TCR1 are ignored. The lower 8 bits cannot be cleared
Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR0 is in accordance with the 16-bit compare
Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR1 is in accordance with the lower 8-bit compare
(TCNT0 and TCNT1 together) is cleared when a 16-bit compare match event occurs. The 16-bit counter (TCNT0
and TCNT1 together) is cleared even if counter clear by the TMRI0 pin has also been set.
independently.
match conditions.
match conditions.
Operation with Cascaded Connection
Rev.6.00 Oct.28.2004 page 445 of 1016
REJ09B0138-0600H
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