DF2398TE20V Renesas Electronics America, DF2398TE20V Datasheet - Page 468
![IC H8S MCU FLASH 256K 120TQFP](/photos/12/21/122170/df2398te20v_sml.jpg)
DF2398TE20V
Manufacturer Part Number
DF2398TE20V
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2398TE20V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit 5—Timer Overflow Interrupt Enable (OVIE): Selects whether OVF interrupt requests (OVI) are enabled or
disabled when the OVF flag of TCSR is set to 1.
Bits 4 and 3—Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select the method by which TCNT is cleared:
by compare match A or B, or by an external reset input.
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to TCNT is an internal or
external clock.
Three internal clocks can be selected, all divided from the system clock (ø): ø/8, ø/64, and ø/8192. The falling edge of the
selected internal clock triggers the count.
When use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and
both rising and falling edges.
Some functions differ between channel 0 and channel 1.
Note: * If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare match
Rev.6.00 Oct.28.2004 page 438 of 1016
REJ09B0138-0600H
signal, no incrementing clock is generated. Do not use this setting.
Bit 5
OVIE
0
1
Bit 4
CCLR1
0
1
Bit 2
CKS2
0
1
Bit 1
CKS1
0
1
0
1
Description
OVF interrupt requests (OVI) are disabled
OVF interrupt requests (OVI) are enabled
Bit 3
CCLR0
0
1
0
1
Bit 0
CKS0
0
1
0
1
0
1
0
1
Description
Clear is disabled
Clear by compare match A
Clear by compare match B
Clear by rising edge of external reset input
Description
Clock input disabled
Internal clock, counted at falling edge of ø/8
Internal clock, counted at falling edge of ø/64
Internal clock, counted at falling edge of ø/8192
For channel 0: count at TCNT1 overflow signal*
For channel 1: count at TCNT0 compare match A*
External clock, counted at rising edge
External clock, counted at falling edge
External clock, counted at both rising and falling edges
(Initial value)
(Initial value)
(Initial value)
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