DF2398TE20V Renesas Electronics America, DF2398TE20V Datasheet - Page 147
![IC H8S MCU FLASH 256K 120TQFP](/photos/12/21/122170/df2398te20v_sml.jpg)
DF2398TE20V
Manufacturer Part Number
DF2398TE20V
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2398TE20V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 147 of 1049
- Download datasheet (5Mb)
Bit 4—2-CAS Method Select (CW2): Write 1 to this bit when areas 2 to 5 are designated as 8-bit DRAM space, and 0
otherwise.
Bits 3 and 2—Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the shift to the lower half of
the row address in row address/column address multiplexing for the DRAM interface. In burst operation on the DRAM
interface, these bits also select the row address to be used for comparison.
Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1, RLW0): These bits select the number of wait states to be
inserted in a DRAM interface CAS-before-RAS refresh cycle. This setting is used for all areas designated as DRAM
space. Wait input by the WAIT pin is disabled.
Bit 4
CW2
0
1
Bit 3
MXC1
0
1
Bit 1
RLW1
0
1
Description
16-bit DRAM space selected
8-bit DRAM space selected
Bit 2
MXC0
0
1
0
1
Bit 0
RLW0
0
1
0
1
Description
8-bit shift
9-bit shift
10-bit shift
—
Description
No wait state inserted
1 wait state inserted
2 wait states inserted
3 wait states inserted
When 8-bit access space is designated: Row address A
for comparison
When 16-bit access space is designated: Row address A
for comparison
When 8-bit access space is designated: Row address A
for comparison
When 16-bit access space is designated: Row address A
for comparison
When 8-bit access space is designated: Row address A
for comparison
When 16-bit access space is designated: Row address A
for comparison
Rev.6.00 Oct.28.2004 page 117 of 1016
23
23
23
23
23
23
(Initial value)
(Initial value)
(Initial value)
to A
to A
to A
to A
to A
to A
8
9
10
REJ09B0138-0600H
9
10
11
used
used
used
used
used
used
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