DF2398TE20V Renesas Electronics America, DF2398TE20V Datasheet - Page 403
![IC H8S MCU FLASH 256K 120TQFP](/photos/12/21/122170/df2398te20v_sml.jpg)
DF2398TE20V
Manufacturer Part Number
DF2398TE20V
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2398TE20V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 403 of 1049
- Download datasheet (5Mb)
Free-running count operation and periodic count operation
Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit
in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT
overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in
TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000.
Figure 10-7 illustrates free-running counter operation.
When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs
periodic count operation. The TGR register for setting the period is designated as an output compare register, and
counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have
been made, TCNT starts up-count operation as periodic counter when the corresponding bit in TSTR is set to 1. When
the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000.
If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare
match, TCNT starts counting up again from H'0000.
Figure 10-8 illustrates periodic counter operation.
H'FFFF
H'0000
CST bit
TCFV
TGR
H'0000
CST bit
TGF
TCNT value
TCNT value
Figure 10-7 Free-Running Counter Operation
Figure 10-8 Periodic Counter Operation
Counter cleared by TGR
compare match
Flag cleared by software or
DTC/DMAC activation
Rev.6.00 Oct.28.2004 page 373 of 1016
Time
Time
REJ09B0138-0600H
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