DF2398TE20V Renesas Electronics America, DF2398TE20V Datasheet - Page 237
![IC H8S MCU FLASH 256K 120TQFP](/photos/12/21/122170/df2398te20v_sml.jpg)
DF2398TE20V
Manufacturer Part Number
DF2398TE20V
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2398TE20V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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7.5.6
In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by
setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA to 0.
In normal mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is
executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination
by MARB.
Table 7-10 summarizes register functions in normal mode.
Table 7-10 Register Functions in Normal Mode
Legend:
MARA: Memory address register A
MARB: Memory address register B
ETCRA: Transfer count register A
MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits.
MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed.
Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB.
The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented each time a transfer is performed, and
when its value reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt
request is sent to the CPU or DTC.
The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536.
Normal Mode
Register
23
23
15
MARA
MARB
ETCRA
0
0
0
Function
Source address
register
Destination
address register
Transfer counter Number of transfers Decremented every
Initial Setting
Start address of
transfer source
Start address of
transfer destination
Rev.6.00 Oct.28.2004 page 207 of 1016
Operation
Incremented/decremented
every transfer, or fixed
Incremented/decremented
every transfer, or fixed
transfer; transfer ends
when count reaches
H'0000
REJ09B0138-0600H
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