DF2398TE20V Renesas Electronics America, DF2398TE20V Datasheet - Page 519
![IC H8S MCU FLASH 256K 120TQFP](/photos/12/21/122170/df2398te20v_sml.jpg)
DF2398TE20V
Manufacturer Part Number
DF2398TE20V
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2398TE20V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 519 of 1049
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14.3.2
In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication
and one or two stop bits indicating the end of communication. Serial communication is thus carried out with
synchronization established on a character-by-character basis.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the
transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission
or reception, enabling continuous data transfer.
Figure 14-2 shows the general format for asynchronous serial communication.
In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI
monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial
communication.
One serial communication character consists of a start bit (low level), followed by data (in LSB-first order), a parity bit
(high or low level), and finally one or two stop bits (high level).
In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples
the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at
the center of each bit.
Data Transfer Format: Table 14-10 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SMR setting.
Operation in Asynchronous Mode
Serial
data
1
Start
bit
1 bit
0
LSB
Figure 14-2 Data Format in Asynchronous Communication
D0
One unit of transfer data (character or frame)
(Example with 8-Bit Data, Parity, Two Stop Bits)
D1
D2
Transmit/receive data
D3
7 or 8 bits
D4
D5
D6
MSB
D7
Parity
bit
1 bit,
or none
0/1
Rev.6.00 Oct.28.2004 page 489 of 1016
Stop bit
1
1 or
2 bits
1
Idle state
(mark state)
1
REJ09B0138-0600H
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