DF2398TE20V Renesas Electronics America, DF2398TE20V Datasheet - Page 497
![IC H8S MCU FLASH 256K 120TQFP](/photos/12/21/122170/df2398te20v_sml.jpg)
DF2398TE20V
Manufacturer Part Number
DF2398TE20V
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2398TE20V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 497 of 1049
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14.1.2
Figure 14-1 shows a block diagram of the SCI.
14.1.3
Table 14-1 shows the serial pins for each SCI channel.
Table 14-1 SCI Pins
Block Diagram
Pin Configuration
Channel
0
1
2
Legend:
SCK
RxD
TxD
SCMR:
RSR:
RDR:
TSR:
TDR:
SMR:
SCR:
SSR:
BRR:
Smart Card mode register
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register
Serial status register
Bit rate register
Pin Name
Serial clock pin 0
Receive data pin 0
Transmit data pin 0
Serial clock pin 1
Receive data pin 1
Transmit data pin 1
Serial clock pin 2
Receive data pin 2
Transmit data pin 2
RDR
RSR
Parity generation
Parity check
Figure 14-1 Block Diagram of SCI
TDR
TSR
Module data bus
Symbol
SCK0
RxD0
TxD0
SCK1
RxD1
TxD1
SCK2
RxD2
TxD2
reception control
Transmission/
SCMR
I/O
I/O
Input
Output
I/O
Input
Output
I/O
Input
Output
SCR
SMR
SSR
External clock
Clock
Function
SCI0 clock input/output
SCI0 receive data input
SCI0 transmit data output
SCI1 clock input/output
SCI1 receive data input
SCI1 transmit data output
SCI2 clock input/output
SCI2 receive data input
SCI2 transmit data output
Baud rate
generator
BRR
Rev.6.00 Oct.28.2004 page 467 of 1016
TEI
TXI
RXI
ERI
ø
ø/4
ø/16
ø/64
data bus
Internal
REJ09B0138-0600H
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