DF2398TE20V Renesas Electronics America, DF2398TE20V Datasheet - Page 562
![IC H8S MCU FLASH 256K 120TQFP](/photos/12/21/122170/df2398te20v_sml.jpg)
DF2398TE20V
Manufacturer Part Number
DF2398TE20V
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2398TE20V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 562 of 1049
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Serial Data Reception: Data reception in Smart Card mode uses the same processing procedure as for the normal SCI.
Figure 15-7 shows an example of the transmission processing flow.
[1] Perform Smart Card interface mode initialization as described above in Initialization.
[2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either is set, perform the appropriate receive error
[3] Repeat steps [2] and [3] until it can be confirmed that the RDRF flag is set to 1.
[4] Read the receive data from RDR.
[5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2].
[6] To end reception, clear the RE bit to 0.
With the above processing, interrupt servicing or data transfer by the DMAC or DTC is possible.
If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive
data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag
is set to 1, a transfer error interrupt (ERI) request will be generated.
If the DMAC or DTC is activated by an RXI request, the receive data in which the error occurred is skipped, and only the
number of bytes of receive data set in the DMAC or DTC are transferred.
For details, see Interrupt Operation and Data Transfer Operation by DMAC or DTC below.
Rev.6.00 Oct.28.2004 page 532 of 1016
REJ09B0138-0600H
processing, then clear both the ORER and the PER flag to 0.
No
No
Figure 15-7 Example of Reception Processing Flow
RDRF flag in SSR to 0
Read RDR and clear
All data received?
Clear RE bit to 0
ORER = 0 and
Start reception
Initialization
RDRF=1?
PER = 0
Start
Yes
Yes
Yes
No
Error processing
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