DF2398TE20V Renesas Electronics America, DF2398TE20V Datasheet - Page 105
![IC H8S MCU FLASH 256K 120TQFP](/photos/12/21/122170/df2398te20v_sml.jpg)
DF2398TE20V
Manufacturer Part Number
DF2398TE20V
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2398TE20V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 105 of 1049
- Download datasheet (5Mb)
4.2.3
The H8S/2357 Group enters the reset state when the RES pin goes low.
To ensure that the H8S/2357 Group is reset, hold the RES pin low for at least 20 ms at power-up. To reset the H8S/2357
Group during operation, hold the RES pin low for at least 20 states.
When the RES pin goes high after being held low for the necessary time, the H8S/2357 Group starts reset exception
handling as follows:
1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, the T bit is cleared to
2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the
Figure 4-2 show examples of the reset sequence.
0 in EXR, and the I bit is set to 1 in EXR and CCR.
address indicated by the PC.
Reset Sequence
RES
Address bus
RD
HWR, LWR
D
(1) (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002)
(2) (4) Start address (contents of reset exception handling vector address)
(5) Start address ((5) = (2) (4))
(6) First program instruction
Note: * 3 program wait states are inserted.
15
to D
ø
0
Figure 4-2 Reset Sequence (Mode 4)
*
(1)
Vector fetch
(2)
High
*
(3)
Internal
processing
(4)
Prefetch of first
program instruction
Rev.6.00 Oct.28.2004 page 75 of 1016
(5)
*
(6)
REJ09B0138-0600H
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