MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 87

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.4.6 Program Page Register
Read: Anytime
Write: Anytime
When enabled (PWEN = 1), the value in this register determines which of the 256 16-Kbyte pages is
active in the program window. An access to the program page memory area ($8000 to $BFFF) forces the
contents of PPAGE to address pins ADDR15–ADDR14 and expansion address pins ADDR21–ADDR16.
At least one of the program chip-selects (CSP0 or CSP1) must be used in conjunction with this memory
expansion window. This register is used by the CALL and RTC instructions to facilitate automatic program
flow changing between pages of program memory.
8.4.7 Extra Page Register
Read: Anytime
Write: Anytime
When enabled (EWEN = 1), the value in this register determines which of the 256 1-Kbyte pages is active
in the extra window. An access to the extra page memory area forces the contents of EPAGE to address
pins ADDR15–ADDR10 and expansion address pins ADDR16–ADDR17. Address bits
ADDR21–ADDR18 are forced to one (if enabled by MXAR). Chip-select 3 set to follow the extra page
window (CS3 with CS3EP = 1) must be used in conjunction with this memory expansion window.
8.4.8 Window Definition Register
Read: Anytime
Write: Anytime
DWEN — Data Window Enable Bit
Freescale Semiconductor
1 = Enables paging of the data space (4 Kbytes: $7000–$7FFF) via the DPAGE register
0 = Disables DPAGE
Address: $0035
Address: $0036
Address: $0037
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
PPA21
PEA17
DWEN
Bit 7
Bit 7
Bit 7
0
0
0
Figure 8-14. Window Definition Register (WINDEF)
Figure 8-12. Program Page Register (PPAGE)
Figure 8-13. Extra Page Register (EPAGE)
PPA20
PEA16
PWEN
6
0
6
0
6
0
MC68HC812A4 Data Sheet, Rev. 7
PPA19
PEA15
EWEN
5
0
5
0
5
0
PPA18
PEA14
4
0
4
0
4
0
0
PPA17
PEA13
3
0
3
0
3
0
0
PPA16
PEA12
2
0
2
0
2
0
0
PPA15
PEA11
1
0
1
0
1
0
0
Memory Expansion Registers
PPA14
PEA10
Bit 0
Bit 0
Bit 0
0
0
0
0
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