MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 53

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Effects of Reset
4.6 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known startup states, as follows.
4.6.1 Operating Mode and Memory Map
The states of the BGND, MODA, and MODB pins during reset determine the operating mode and default
memory mapping. The SMODN, MODA, and MODB bits in the MODE register reflect the status of the
mode-select inputs at the rising edge of reset. Operating mode and default maps can subsequently be
changed according to strictly defined rules.
4.6.2 Clock and Watchdog Control Logic
Reset enables the COP watchdog with the CR2–CR0 bits set for the longest timeout period. The clock
monitor is disabled. The RTIF flag is cleared and automatic hardware interrupts are masked. The rate
control bits are cleared, and must be initialized before the RTI system is used. The DLY control bit is set
to specify an oscillator startup delay upon recovery from stop mode.
4.6.3 Interrupts
Reset initializes the HPRIO register with the value $F2, causing the IRQ pin to have the highest I bit
interrupt priority. The IRQ pin is configured for level-sensitive operation (for wired-OR systems). However,
the I and X bits in the CCR are set, masking IRQ and XIRQ interrupt requests.
4.6.4 Parallel I/O
If the MCU comes out of reset in an expanded mode, port A and port B are the address bus. Port C and
port D are the data bus. In narrow mode, port C alone is the data bus. Port E pins are normally used to
control the external bus. The PEAR register affects port E pin operation.
If the MCU comes out of reset in a single-chip mode, all ports are configured as general-purpose,
high-impedance inputs except in normal narrow expanded mode (NNE). In NNE, PE3 is configured as an
output driven high.
In expanded modes, PF5 is an active chip-select.
4.6.5 Central Processor Unit
After reset, the CPU fetches a vector from the appropriate address and begins executing instructions. The
stack pointer and other CPU registers are indeterminate immediately after reset. The CCR X and I
interrupt mask bits are set to mask any interrupt requests. The S bit is also set to inhibit the STOP
instruction.
4.6.6 Memory
After reset, the internal register block is located at $0000–$01FF and RAM is at $0800–$0BFF. EEPROM
is located at $1000–$1FFF in expanded modes and at $F000–$FFFF in single-chip modes.
4.6.7 Other Resources
The timer, serial communications interface (SCI), serial peripheral interface (SPI), and analog-to-digital
converter (ATD) are off after reset.
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor
53