MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 172

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Serial Communications Interface Module (SCI)
SBK — Send Break Bit
14.6.4 SCI Status Register 1
Read: Anytime
Write: Has no meaning or effect
TDRE — Transmit Data Register Empty Flag
TC — Transmission Complete Flag
RDRF — Receive Data Register Full Flag
IDLE — Idle Line Flag
172
Toggling SBK sends one break character (10 or 11 logic 0s). As long as SBK is set, the transmitter
sends logic 0s.
TDRE is set when the transmit shift register receives a byte from the SCI data register. Clear TDRE
by reading SCI status register 1 with TDRE set and then writing to the low byte of the SCI data register.
TC is set when the TDRE flag is set and no data, preamble, or break character is being transmitted.
When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 with TC
set and then writing to the low byte of the SCI data register. TC clears automatically when a break,
preamble, or data is queued and ready to be sent.
RDRF is set when the data in the receive shift register transfers to the SCI data register. Clear RDRF
by reading SCI status register 1 with RDRF set and then reading the low byte of the SCI data register.
IDLE is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M = 1) appear on the
receiver input. Clear IDLE by reading SCI status register 1 with IDLE set and then writing to the low
byte of the SCI data register. Once IDLE is cleared, a valid frame must again set the RDRF flag before
an idle condition can set the IDLE flag.
1 = Transmit break characters
0 = No break characters
1 = Transmit data register empty
0 = Transmit date register not empty
1 = Transmission complete
0 = Transmission in progress
1 = Receive data register full
0 = Data not available in SCI data register
1 = Receiver input has become idle
0 = Receiver input is either active now or has never become active since the IDLE flag was last
cleared
Reset:
Read:
Write:
SCI0: $00C4
SCI1: $00CC
When the receiver wakeup bit (RWU) is set, an idle line condition does not
set the IDLE flag.
TDRE
Figure 14-21. SCI Status Register 1 (SC0SR1 or SC1SR1)
Bit 7
1
= Unimplemented
TC
6
1
MC68HC812A4 Data Sheet, Rev. 7
RDRF
5
0
IDLE
NOTE
4
0
OR
3
0
NF
2
0
FE
1
0
Freescale Semiconductor
Bit 0
PF
0