MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 189

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.6.4 SPI Status Register
Read: Anytime
Write: Has no meaning or effect
SPIF — SPI Flag
WCOL — Write Collision Flag
MODF — Mode Fault Flag
Freescale Semiconductor
SPIF is set after the eighth serial clock cycle of a transmissson. SPIF generates an interrupt request if
the SPIE bit in SPI control register 1 is set also. Clear SPIF by reading the SPI status register with SPIF
set and then reading or writing to the SPI data register.
WCOL is set when a write to the SPI data register occurs during a data transfer. The byte being
transferred continues to shift out of the shift register, and the data written during the transfer is lost.
WCOL does not generate an interrupt request. WCOL can be read when the transfer in progress is
complete. Clear WCOL by reading the SPI status register with WCOL set and then reading or writing
to the SPI data register.
MODF is set if the PS7 pin goes to logic 0 when it is configured as the SS input of a master SPI
(MSTR = 1 and DDR7 = 0). Clear MODF by reading the SPI status register with MODF set and then
writing to SPI control register 1.
1 = Transfer complete
0 = Transfer not complete
1 = Write collision
0 = No write collision
1 = Mode fault
0 = No mode fault
Address: $00D3
MODF is inhibited when the PS7 pin is configured as:
Reset:
Read:
Write:
• The SS output, DDRS7 = 1 and SSOE = 1, or
• A general-purpose output, DDRS7 = 1 and SSOE = 0
SPIF
Bit 7
0
= Unimplemented
Figure 15-12. SPI Status Register (SP0SR)
WCOL
6
0
MC68HC812A4 Data Sheet, Rev. 7
5
0
0
MODF
NOTE
4
0
3
0
0
SPI Register Descriptions and Reset Initialization
2
0
0
1
0
0
Bit 0
0
0
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