MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 101

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 10
Clock Module
10.1 Introduction
Clock generation circuitry generates the internal and external E-clock signals as well as internal clock
signals used by the CPU and on-chip peripherals. A clock monitor circuit, a computer operating properly
(COP) watchdog circuit, and a periodic interrupt circuit are also incorporated into the MCU.
10.2 Block Diagram
10.2.1 Clock Generators
The clock module generates four types of internal clock signals derived from the oscillator:
Freescale Semiconductor
XTAL
1. T-clocks — Drives the CPU
2. E-clock — Drives the bus interfaces, BDM, SPI, and ATD
3. P-clock — Drives the bus interfaces, BDM, SPI, and ATD
4. M-clock — Drives on-chip modules such as the timer, SCI, RTI, COP, and restart-from-stop delay
OSCILLATOR
time
PHASE-LOCK
PLLS
EXTAL
LOOP
MUXCLK
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
Figure 10-1. Clock Module Block Diagram
REGISTER: CLKCTL
BITS: BCS[C:B:A]
MC68HC812A4 Data Sheet, Rev. 7
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
SYSCLK
÷ 2
E- AND P-CLOCK
GENERATOR
GENERATOR
T-CLOCK
÷ 2
÷ 2
÷ 2
÷ 2
REGISTER: CLKCTL
BITS: MCS[B:A]
0:0
0:1
1:0
1:1
TCLK
ECLK
PCLK
MCLK
TO CPU
TO BDM,
BUSES,
SPI,
ATD
TO SCI, TIM,
PA, RTI, COP
101