C8051F321-GM Silicon Laboratories Inc, C8051F321-GM Datasheet - Page 57

• Manufacturer Part Number: C8051F321-GM
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321-GM

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C/SMBus/SPI/UART/USB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F320DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit or 17-ch x 10-bit
• No. Of I/o's: 21
• Ram Memory Size: 1280Byte
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1480 - DAUGHTER CARD TOOLSTCK C8051F321770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1449 - ADAPTER PROGRAM TOOLSTICK F321336-1260 - DEV KIT FOR C8051F320/F321
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1261

7.
C8051F320/1 devices include two on-chip programmable voltage Comparators: Comparator0 is shown in Figure 7.1;
Comparator1 is shown in Figure 7.2. The two Comparators operate identically with the following exceptions: (1)
Their input selections differ as shown in Figure 7.1 and Figure 7.2; (2) Comparator0 can be used as a reset source.
Each Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs
that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an asynchronous “raw”
output (CP0A, CP1A). The asynchronous signal is available even when the system clock is not active. This allows the
Comparators to operate and generate an output with the device in STOP mode. When assigned to a Port pin, the Com-
parator outputs may be configured as open drain or push-pull (see
page
The Comparator0 inputs are selected in the CPT0MX register (Figure 7.5). The CMX0P1-CMX0P0 bits select the
Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative input. The Comparator1
inputs are selected in the CPT1MX register (Figure 7.8). The CMX1P1-CMX1P0 bits select the Comparator1 posi-
tive input; the CMX1N1-CMX1N0 bits select the Comparator1 negative input.
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be configured as
analog inputs in their associated Port configuration register, and configured to be skipped by the Crossbar (for details
on Port configuration, see
131). Comparator0 may also be used as a reset source (see
CMX0N1
CMX0N0
CMX0P1
CMX0P0
COMPARATORS
Note: P2.4 and P2.5 available
only on C8051F320
P1.0
P1.4
P2.0
P2.4
P1.1
P1.5
P2.1
P2.5
Figure 7.1. Comparator0 Functional Block Diagram
Section “14.3. General Purpose Port I/O” on page
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP0OUT
CP0RIF
CP0FIF
CP0EN
CP0 +
CP0 -
CP0MD1
CP0MD0
CP0RIE
CP0FIE
+
-
GND
VDD
Rev. 1.1
Section “10.5. Comparator0 Reset” on page
Decision
Reset
Tree
(SYNCHRONIZER)
D
SET
CLR
Section “14.2. Port I/O Initialization” on
Q
Q
D
SET
CLR
Q
Q
134).
Rising-edge
CP0
C8051F320/1
Crossbar
Interrupt
Logic
Falling-edge
Interrupt
CP0
CP0A
CP0
CP0
CP0RIE
CP0FIE
102).
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