C8051F321-GM Silicon Laboratories Inc, C8051F321-GM Datasheet - Page 12

• Manufacturer Part Number: C8051F321-GM
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321-GM

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C/SMBus/SPI/UART/USB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F320DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit or 17-ch x 10-bit
• No. Of I/o's: 21
• Ram Memory Size: 1280Byte
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1480 - DAUGHTER CARD TOOLSTCK C8051F321770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1449 - ADAPTER PROGRAM TOOLSTICK F321336-1260 - DEV KIT FOR C8051F320/F321
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1261

C8051F320/1
15. UNIVERSAL SERIAL BUS CONTROLLER (USB0) ...................................................143
16. SMBUS .................................................................................................................................175
12
Figure 14.16. P2MDIN: Port2 Input Mode Register .............................................................139
Figure 14.17. P2MDOUT: Port2 Output Mode Register.......................................................140
Figure 14.18. P2SKIP: Port2 Skip Register...........................................................................140
Figure 14.19. P3: Port3 Register............................................................................................141
Figure 14.20. P3MDIN: Port3 Input Mode Register .............................................................141
Figure 14.21. P3MDOUT: Port3 Output Mode Register.......................................................142
Table 14.1. Port I/O DC Electrical Characteristics ..............................................................142
Figure 15.1. USB0 Block Diagram........................................................................................143
Table 15.1. Endpoint Addressing Scheme............................................................................144
Figure 15.2. USB0XCN: USB0 Transceiver Control............................................................145
Figure 15.3. USB0 Register Access Scheme .........................................................................146
Figure 15.4. USB0ADR: USB0 Indirect Address Register ...................................................147
Figure 15.5. USB0DAT: USB0 Data Register ......................................................................148
Figure 15.6. INDEX: USB0 Endpoint Index (USB Register) ...............................................148
Table 15.2. USB0 Controller Registers ................................................................................149
Figure 15.7. CLKREC: Clock Recovery Control (USB Register) ........................................150
Figure 15.8. USB FIFO Allocation........................................................................................151
Table 15.3. FIFO Configurations .........................................................................................152
Figure 15.9. FIFOn: USB0 Endpoint FIFO Access (USB Registers) ...................................152
Figure 15.10. FADDR: USB0 Function Address (USB Register) ........................................153
Figure 15.11. POWER: USB0 Power (USB Register) ..........................................................155
Figure 15.12. FRAMEL: USB0 Frame Number Low (USB Register) .................................156
Figure 15.13. FRAMEH: USB0 Frame Number High (USB Register) ................................156
Figure 15.14. IN1INT: USB0 IN Endpoint Interrupt (USB Register)...................................157
Figure 15.15. OUT1INT: USB0 Out Endpoint Interrupt (USB Register).............................158
Figure 15.16. CMINT: USB0 Common Interrupt (USB Register)........................................159
Figure 15.17. IN1IE: USB0 IN Endpoint Interrupt Enable (USB Register) .........................160
Figure 15.18. OUT1IE: USB0 Out Endpoint Interrupt Enable (USB Register)....................160
Figure 15.19. CMIE: USB0 Common Interrupt Enable (USB Register) ..............................161
Figure 15.20. E0CSR: USB0 Endpoint0 Control (USB Register) ........................................164
Figure 15.21. E0CNT: USB0 Endpoint 0 Data Count (USB Register) .................................165
Figure 15.22. EINCSRL: USB0 IN Endpoint Control High Byte (USB Register) ...............168
Figure 15.23. EINCSRH: USB0 IN Endpoint Control Low Byte (USB Register) ...............169
Figure 15.24. EOUTCSRL: USB0 OUT Endpoint Control High Byte (USB Register) .......171
Figure 15.25. EOUTCSRH: USB0 OUT Endpoint Control Low Byte (USB Register) .......172
Figure 15.26. EOUTCNTL: USB0 OUT Endpoint Count Low (USB Register) ..................172
Figure 15.27. EOUTCNTH: USB0 OUT Endpoint Count High (USB Register) .................172
Table 15.4. USB Transceiver Electrical Characteristics ......................................................173
Figure 16.1. SMBus Block Diagram .....................................................................................175
Figure 16.2. Typical SMBus Configuration ..........................................................................176
Figure 16.3. SMBus Transaction ...........................................................................................177
Table 16.1. SMBus Clock Source Selection.........................................................................180
Figure 16.4. Typical SMBus SCL Generation.......................................................................181
Rev. 1.1