C8051F321-GM Silicon Laboratories Inc, C8051F321-GM Datasheet - Page 114

IC 8051 MCU 16K FLASH 28MLP

C8051F321-GM

Manufacturer Part Number
C8051F321-GM
Description
IC 8051 MCU 16K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F32xr
Datasheets

Specifications of C8051F321-GM

Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
21
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2.25 KB
Interface Type
I2C/SMBus/SPI/UART/USB
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
21
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F320DK
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit or 17-ch x 10-bit
No. Of I/o's
21
Ram Memory Size
1280Byte
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1480 - DAUGHTER CARD TOOLSTCK C8051F321770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1449 - ADAPTER PROGRAM TOOLSTICK F321336-1260 - DEV KIT FOR C8051F320/F321
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1261

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C8051F320/1
12.2. Accessing USB FIFO Space
The upper 1k of XRAM functions as USB FIFO space. Figure 12.2 shows an expanded view of the FIFO space and
user XRAM. FIFO space is accessed via USB FIFO registers; see
for more information on accessing these FIFOs. The MOVX instruction should not be used to load or modify USB
data in the FIFO space.
Unused areas of the FIFO space may be used as general purpose XRAM, accessible as described in
FIFO block operates on the USB clock domain; thus the USB clock must be active when accessing FIFO space. Note
that the number of SYSCLK cycles required by the MOVX instruction is increased when accessing USB FIFO space.
Important Note: The USB clock must be active when accessing FIFO space.
114
User XRAM Space
(System Clock Domain)
0x03FF
Figure 12.2. XRAM Memory Map Expanded View
0x0000
(1024 bytes)
User XRAM
Rev. 1.1
0x07C0
0x07BF
0x07FF
0x0740
0x073F
0x0640
0x063F
0x0440
0x043F
0x0400
Section “15.5. FIFO Management” on page 151
(128 bytes)
(256 bytes)
(512 bytes)
Endpoint0
Endpoint1
Endpoint2
Endpoint3
(64 bytes)
(64 bytes)
Free
USB FIFO Space
(USB Clock Domain)
Section
12.1. The

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