Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 52

MCU 8BIT 24KB FLASH 44LQFP

Z8F2480AN020SG

Manufacturer Part Number
Z8F2480AN020SG
Description
MCU 8BIT 24KB FLASH 44LQFP
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheets

Specifications of Z8F2480AN020SG

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
Number Of I /o
37
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-LQFP
Processor Series
Z8F248x
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
37
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 8 Channel
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
269-4676

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8F2480AN020SG
Manufacturer:
Zilog
Quantity:
85
Part Number:
Z8F2480AN020SG
Manufacturer:
Zilog
Quantity:
10 000
PS025011-1010
Note: Not to Scale
System Clock
Internal Reset
WDT Clock
Internal VBO
V
DD
Signal
Reset
Watchdog Timer Reset
External Reset Input
= 3.3 V
V
V
VBO+
VBO
If the device is in NORMAL or STOP mode, WDT initiates a System Reset at 
timeout if the
state of the
WDT to cause an interrupt, not a System Reset at timeout. The WDT status bit in the Reset
Status Register is set to signify that the reset was initiated by the WDT.
The RESET pin has a Schmitt-triggered input and an internal pull-up resistor. When the
RESET pin is asserted for a minimum of four system clock cycles, the device progresses
through the System Reset sequence. Because of the possible asynchronicity of the system
Execution
Program
VBO delay: pulse rejection
WDT_RES
Figure 8. Voltage Brownout Reset Operation
WDT_RES
Brownout
Flash Option Bit. If the bit is programmed to 0, it configures the
Voltage
Flash Option Bit is programmed to 1. This is the unprogrammed
P R E L I M I N A R Y
counter delay
POR
Reset, Stop Mode Recovery, and Low-Voltage
Z8 Encore! XP
Product Specification
Execution
Program
®
F1680 Series
V
DD
= 3.3 V
38

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