Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 193

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
Baud Rate
IR_RXD
UART’s
Clock
RXD
Caution:
Receiving IrDA Data
8-clock
delay
Start Bit = 0
Data received from the infrared transceiver using the
is decoded by the Infrared Endec and passed to the UART. The UART’s baud rate clock is
used by the Infrared Endec to generate the demodulated signal (
UART. Each UART/Infrared data bit is 16 clocks wide.
When the Infrared Endec is enabled, the UART’s
Z8 Encore! XP F1680 Series products while the
RXD pin.
Infrared Data Reception
Endec Receiver Synchronization
The IrDA receiver uses a local baud rate clock counter (0 to 15 clock periods) to generate
an input stream for the UART and to create a sampling window for detection of incoming
pulses. The generated UART input (UART RXD) is delayed by 8 baud rate clock periods
with respect to the incoming IrDA data stream. When a falling edge in the input data
stream is detected, the Endec counter is reset. When the count reaches a value of 8, the
UART RXD value is updated to reflect the value of the decoded data. When the count
reaches 12 baud clock periods, the sampling window for the next incoming pulse opens.
16-clock
min. 1.4
period
The system clock frequency must be at least 1.0 MHz to ensure proper reception of the
1.4
pulse

Start Bit = 0
s minimum width pulses allowed by the IrDA standard.

16-clock
s
period
Data Bit 0 = 1
Figure 29. IrDA Data Reception
Data Bit 0 = 1
P R E L I M I N A R Y
16-clock
period
Data Bit 1 = 0
Data Bit 1 = 0
16-clock
period
IR_RXD
RXD
Data Bit 2 = 1
IR_RXD
signal is internal to the
Z8 Encore! XP
Figure 29
signal is received through the
Data Bit 2 = 1
signal through the RXD pin
16-clock
RXD
period
Product Specification
displays data reception.
Infrared Encoder/Decoder
) that drives the
Data Bit 3 = 1
®
F1680 Series
Data Bit 3 = 1
179