Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 231

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
Operation
SDA and SCL Signals
Table 119. I
The I
mode, or with master arbitration. In MASTER/SLAVE mode, it can be used as the only
Master on the bus or as one of the several masters on the bus, with arbitration. In a 
Multi-Master environment, the controller switches from MASTER to SLAVE mode on
losing arbitration.
Though slave operation is fully supported in MASTER/SLAVE mode, if a device is
intended to operate only as a slave, then SLAVE ONLY mode can be selected. In SLAVE
ONLY mode, the device will not initiate a transaction, even if the software inadvertently
sets the START bit.
The I
with most-significant bit first. SCL is the clock for the I
pin alternate functions are selected for their respective GPIO ports, the pins are
automatically configured for open-drain operation.
The Master is responsible for driving the SCL clock signal. During the Low period of the
clock, a slave can hold the SCL signal Low to suspend the transaction if it is not ready to
proceed. The Master releases the clock at the end of the Low period and notices that the
clock remains Low instead of returning to a High level. When the slave releases the clock,
the I
the amount of data transferred in one operation. When transmitting address, data, or an
Acknowledge, the SDA signal changes in the middle of the Low period of SCL
receiving address, Data, or an Acknowledge; the SDA signal is sampled in the middle of
the High period of SCL.
Name
I
I
I
I
I
I
2
2
2
2
2
2
C State
C Control
C Baud Rate High I2CBRH
C Baud Rate Low I2CBRL
C Mode
C Slave Address I2CSLVAD
2
2
2
C master continues the transaction. All data is transferred in bytes; there is no limit to
C Master/Slave Controller operates in MASTER/SLAVE mode, SLAVE ONLY
C circuit sends all addresses, Data, and Acknowledge signals over the SDA line,
2
C Master/Slave Controller Registers (Continued)
I2CCTL
I2CSTATE
I2CMODE
Abbreviation
P R E L I M I N A R Y
Description
Control register—basic control functions.
High byte of baud rate generator initialization value.
Low byte of baud rate generator initialization value.
State register.
Selects MASTER or SLAVE modes, 7-bit or 10-bit
addressing; configure address recognition, define
slave address bits [9:8].
Defines slave address bits [7:0].
Z8 Encore! XP
2
C bus. When the SDA and SCL
Product Specification
I2C Master/Slave Controller
®
F1680 Series
.
When
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