Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 258

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
I
2
C Slave Address Register
Slave address.
01 = MASTER/SLAVE capable (supports multi-master arbitration) 
with 10-bit slave address.
10 = SLAVE ONLY capable with 7-bit address.
11 = SLAVE ONLY capable with 10-bit address.
IRM—Interactive Receive Mode
Valid in SLAVE mode when software needs to interpret each received byte before
acknowledging. This bit is useful for processing the data bytes following a General Call
Address or if software wants to disable hardware address recognition.
0 = Acknowledge occurs automatically and is determined by the value of the
of the I2CCTL Register.
1 = A receive interrupt is generated for each byte received (address or data). The SCL is
held Low during the Acknowledge cycle until software writes to the I2CCTL Register.
The value written to the
allows software to Acknowledge or Not Acknowledge after interpreting the associated
address/data byte.
GCE—General Call Address Enable
Enables reception of messages beginning with the General Call Address or START byte.
0 = Do not accept a message with the General Call Address or START byte.
1 = Do accept a message with the General Call Address or START byte. When an address
match occurs, the GCA and RD bits in the I
address matched the General Call Address/START byte or not. Following the General Call
Address byte, the software may set the
ing data byte(s) before acknowledging.
SLA[9:8]
Initialize with the appropriate slave address value when using 10-bit slave addressing.
These bits are ignored when using 7-bit slave addressing.
DIAG—Diagnostic Mode 
Selects read back value of the Baud Rate Reload and State registers. 
0 = Reading the Baud Rate registers returns the Baud Rate register values. Reading the
State register returns I
1 = Reading the Baud Rate registers returns the current value of the baud 
rate counter. Reading the State register returns additional state information.
The I
address bits used in 7 and 10 bit slave address recognition.
2
C Slave Address Register (see
— Slave Address Bits 9 and 8 
2
C controller state information.
NAK
P R E L I M I N A R Y
bit of the I2CCTL Register is output on SDA. This value
Table 130)
IRM
2
bit that allows software to examine the follow-
C Status Register indicates whether the
provides control over the lower order
Z8 Encore! XP
Product Specification
I2C Master/Slave Controller
®
F1680 Series
NAK
bit 
244