Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 182

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
MPEN
0 = Disable MULTIPROCESSOR (9-bit) mode.
1 = Enable MULTIPROCESSOR (9-bit) mode.
MULTIPROCESSOR Mode (MPMD[1:0])—MULTIPROCESSOR (9-bit) 
mode—bits 7 and 5.
Multiprocessor (9-Bit) Enable (MPEN)—This bit is used to enable |
MULTIPROCESSOR (9-bit) mode.
Multiprocessor Bit Transmit (MPBT)—This bit is applicable only when 
MULTIPROCESSOR (9-bit) mode is enabled.
Driver Enable Polarity (DEPOL)—See the bit descriptions in
Baud Rate Generator Control (BRGCTL)—This bit causes different LIN-UART
behavior depending on whether the LIN-UART receiver is enabled (REN = 1 in the 
LIN-UART Control 0 Register). When the LIN-UART receiver is not enabled, this bit
determines whether the Baud Rate Generator issues interrupts. When the LIN-UART
receiver is enabled, this bit allows Reads from the baud rate registers to return the BRG
count value instead of the reload value.
Receive Data Interrupt Enable (RDAIRQ)—See the bit descriptions 
in
Infrared Encoder/Decoder Enable (IREN)—See the bit descriptions 
in
10 = The LIN-UART generates an interrupt request when a received address byte matches
MPMD [1:0]—MULTIPROCESSOR Mode
00 = The LIN-UART generates an interrupt request on all received bytes 
01 = The LIN-UART generates an interrupt request on all received address bytes.
11 = The LIN-UART generates an interrupt request on all received data bytes for the most 
Table 90
Table 90
(data and address).
the value stored in the Address Compare Register and on all successive data bytes
until an address mismatch occurs.
recent address byte which matches the value in the Address Compare Register.
—
Multiprocessor Enable
on page 166.
on page 166.
P R E L I M I N A R Y
Z8 Encore! XP
Table 90
Product Specification
®
on page 166.
F1680 Series
LIN-UART
168