Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 176

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
FE
0 = No framing error occurred.
1 = A framing error occurred.
BRKD
0 = No LIN break occurred.
1 = LIN break occurred.
TDRE
0 = Do not write to the Transmit Data Register.
1 = The Transmit Data Register is ready to receive an additional byte for transmission.
TXE
0 = Data is currently transmitting.
1 = Transmission is complete.
ATB— LIN Slave Autobaud complete.
Receive Data Available (RDA)—This bit indicates that the Receive Data Register has
received data. Reading the Receive Data Register clears this bit.
Physical Layer Error (PLE)—This bit indicates that transmit and receive data do not
match when a LIN slave or master is transmitting. This could be by a fault in the physical
layer or multiple devices driving the bus simultaneously. Reading the Status 0 Register or
the Receive Data Register clears this bit.
Receive Data and Autobaud Overrun Error (OE)—This bit is set just as in normal
UART operation if a receive data overrun error occurs. This bit is also set during LIN
Slave autobaud if the BRG counter overflows before the end of the autobaud sequence.
This indicates that the receive activity is not an autobaud character or the master baud rate
is too slow. The ATB status bit will also be set in this case. This bit is cleared by reading
the Receive Data Register.
Framing Error (FE)—This bit indicates that a framing error (no STOP bit following data
reception) is detected. Reading the Receive Data Register clears this bit.
Break Detect (BRKD)—This bit is set in LIN mode if:
Transmitter Data Register Empty (TDRE)—This bit indicates that the Transmit Data
Register is empty and ready for additional data. Writing to the Transmit Data Register
resets this bit.
Transmitter Empty (TXE)—This bit indicates that the transmit shift register is empty
and character transmission is completed.
1. It is in Lin Sleep state and a break of at least 4 bit times occurred (Wake-up event) or
2. It is in Slave Wait Break state and a break of at least 11 bit times occurred 
3. It is in Slave Active state and a break of at least 10 bit times occurs. Reading the
—
—
Framing Error
(Break event) or
Status 0 Register or the Receive Data Register clears this bit.
—
—
Transmitter Empty
Transmitter Data Register Empty
Break Detect
P R E L I M I N A R Y
Z8 Encore! XP
Product Specification
®
F1680 Series
LIN-UART
162