Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 127
Z8F2480AN020SG
Manufacturer Part Number
Z8F2480AN020SG
Description
MCU 8BIT 24KB FLASH 44LQFP
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F2480AN020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
Number Of I /o
37
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-LQFP
Processor Series
Z8F248x
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
37
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 8 Channel
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4676
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F2480AN020SG
Manufacturer:
Zilog
Quantity:
85
- Current page: 127 of 399
- Download datasheet (19Mb)
PS025011-1010
PWM Dual Output mode
CAPTURE RESTART mode
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
CAMPARATOR COUNTER mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
Triggered ONE-SHOT mode
0 = Timer counting is triggered on the rising edge of the Timer Input signal.
1 = Timer counting is triggered on the falling edge of the Timer Input signal.
DEMODULATION mode
0 = Timer counting is triggered on the rising edge of the Timer Input signal.
1 = Timer counting is triggered on the falling edge of the Timer Input signal.
The above functionality applies only if TPOLHI bit in Timer Control 2 register is 0.
If TPOLHI bit is 1 then timer counting is triggered on any edge of the Timer Input
signal and the current count is captured on both edges. The current count is captured
into PWM0 registers on rising edges and PWM1 registers on falling edges of the
Timer Input signal.
The current count is captured into PWM0 High and Low byte registers
on subsequent rising edges of the Timer Input signal.
The current count is captured into PWM1 High and Low byte registers
0 = Timer Output is forced Low (0) and Timer Output Complement is forced
1 = Timer Output is forced High (1) and Timer Output Complement is forced
on subsequent falling edges of the Timer Input signal.
Output Complement is forced to Low (0).
High (1) when the timer is disabled. When enabled, the Timer Output is
forced High (1) upon PWM count match and forced Low (0) upon
Reload. When enabled, the Timer Output Complement is forced Low (0)
upon PWM count match and forced High (1) upon Reload. The PWMD field
in Timer Control 0 register is a programmable delay to control the number
of cycles time delay before the Timer Output and the Timer Output
Complement is forced to High (1).
Low (0) when the timer is disabled. When enabled, the Timer Output is
forced Low (0) upon PWM count match and forced High (1) upon
Reload. When enabled, the Timer Output Complement is forced High (1)
upon PWM count match and forced Low (0) upon Reload. The PWMD
field in Timer Control 0 register is a programmable delay to control the
number of cycles time delay before the Timer Output and the Timer
P R E L I M I N A R Y
Z8 Encore! XP
Product Specification
®
F1680 Series
Timers
113
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