Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 252
Z8F2480AN020SG
Manufacturer Part Number
Z8F2480AN020SG
Description
MCU 8BIT 24KB FLASH 44LQFP
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F2480AN020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
Number Of I /o
37
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-LQFP
Processor Series
Z8F248x
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
37
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 8 Channel
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4676
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F2480AN020SG
Manufacturer:
Zilog
Quantity:
85
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Table 122. I
PS025011-1010
BITS
FIELD
RESET
R/W
ADDR
Note:
2
C Control Register (I2CCTL)
R/W
IEN
7
0
The R/W1 bit may be set (written to 1), when IEN = 1, but cannot be cleared
(written 1 or 0) anyway.
IEN—I
This bit enables the I
START—Send
When set, this bit causes the I
START
the
writing to the bit. After this bit is set, a
I2CDATA or I
controller waits until data is loaded. If this bit is set while the I
data, it generates a
completes. If the
START
device, the START bit will be cleared and ARBLST bit in the Interrupt Status Register
will be set.
STOP—Send
When set, this bit causes the I
STOP
a byte is received in a receive operation. When set, this bit is reset by the I
after a
be cleared to 0 by writing to the register. If STOP is set while a SLAVE mode transaction
is underway, the STOP bit is cleared by hardware.
BIRQ—Baud Rate Generator Interrupt Request
This bit is ignored when the I
controller is disabled (
causing an interrupt to occur every time the baud rate generator counts down to one. The
baud rate generator runs continuously in this mode, generating periodic interrupts.
TXI—Enable TDRE interrupts
This bit enables interrupts when the I
START
condition after the byte in the I
STOP
condition. After it is asserted, this bit is cleared by the I
condition. If START is set while a SLAVE mode transaction is underway to this
2
START
C Enable
R/W1
condition or by deasserting the
6
0
condition has been sent or by deasserting the
2
STOP
C Shift Register. If there is no data in one of these registers, the I
START
STOP
RESTART
2
condition
STOP
R/W1
C controller.
IEN
5
0
bit is also set, it waits till the
condition
= 0), the baud rate generator is used as an additional timer
P R E L I M I N A R Y
condition after the byte shifts and the Acknowledge phase
2
2
2
C controller is enabled. If this bit is set = 1 when the I
C controller (when configured as the master) to send a
C controller (when configured as the master) to send the
BIRQ
R/W
4
0
2
2
C Shift Register has completed transmission or after
C Data Register is empty.
F52H
START
IEN
R/W
TXI
condition is sent if there is data in the
bit. If this bit is 1, it cannot be cleared by
3
0
STOP
Z8 Encore! XP
R/W1
NAK
IEN
condition is sent before the
2
0
2
bit. If this bit is 1, it cannot
2
C controller is shifting out
C controller after it sends
Product Specification
I2C Master/Slave Controller
FLUSH
W
1
0
®
2
F1680 Series
C controller
2
FILTEN
C
R/W
0
0
2
C
238
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