Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 125

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 61. Timer 0–2 Control 1 Register (TxCTL1)
PS025011-1010
BITS
FIELD
RESET
R/W
ADDR
TEN
R/W
7
0
CSC—Cascade Timers
0 = Timer Input signal comes from the pin. 
1 = For Timer 0, Input signal is connected to Timer 2 output.
PWMD—PWM Delay Value
This field is a programmable delay to control the number of timer clock cycles time delay
before the Timer Output and the Timer Output Complement is forced to their active state.
000 = No delay
001 = 2 cycles delay
010 = 4 cycles delay
011 = 8 cycles delay
100 = 16 cycles delay
101 = 32 cycles delay
110 = 64 cycles delay
111 = 128 cycles delay
INPCAP—Input Capture Event
This bit indicates if the last timer interrupt is due to a Timer Input Capture Event.
0 = Previous timer interrupt is not a result of Timer Input Capture Event
1 = Previous timer interrupt is a result of Timer Input Capture Event
Timer 0–2 Control 1 Register
The Timer 0–2 Control 1 (TxCTL1) registers enable/disable the timers, set the prescaler
value, and determine the timer operating mode.
TEN—Timer Enable
0 = Timer is disabled.
1 = Timer enabled to count.
TPOL—Timer Input/Output Polarity
Operation of this field is a function of the current operating modes of the timer.
For Timer 1, Input signal is connected to Timer 0 output.
For Timer 2, Input signal is connected to Timer 1 output.
TPOL
R/W
6
0
R/W
5
0
P R E L I M I N A R Y
F07H, F0FH, F17H
PRES
R/W
4
0
R/W
3
0
Z8 Encore! XP
R/W
2
0
Product Specification
TMODE
R/W
1
0
®
F1680 Series
R/W
0
0
Timers
111